1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and in particular, to the structure of plugs used to connect an upper conductor to a lower conductor and a method for forming plugs, as well as a method for forming a capacitor having a trench structure.
2. Description of the Related Art
In recent years, semiconductor devices have been more and more highly integrated, requiring more precise micromachining. The semiconductor devices require a plug to be formed in an interlayer insulating film in order to connect an upper interconnection layer and a lower interconnection layer together. The plug is normally formed by forming a hole in the interlayer insulating film by dry etching and filling the hole with a conductive material. However, a decrease in the planar area in which the hole can be formed has made the machining based on dry etching significantly difficult.
This difficulty will be described in further detail taking a DRAM (Dynamic Random Access Memory) shown in FIG. 1 as an example.
An n well 102 is formed in a p-type silicon substrate 101. A first p well 103 is formed inside the n well 102. A second p well 104 is formed in the area except for the n well 102. An element isolation region 105 is formed around the p well on a front surface side of the silicon substrate. For convenience, the first p well 103 shows a memory cell region in which a plurality of memory cells are located. The second p well 104 shows a peripheral circuit region.
Switching transistors 106 and 107 are provided in the first p well 103 and each has a gate serving as a word line that is a component of each memory cell. The transistor 106 is composed of a drain 108, a source 109, and a gate electrode 111 provided on the silicon substrate via a gate insulating film 110. The transistor 107 is composed of a source 109 shared by the transistor 106, a drain 112 and a gate electrode 111 provided on the silicon substrate via the gate insulating film 110. An interlayer insulating film 113 with a flat surface covers the transistors.
A contact hole 114 is formed in a predetermined region of the interlayer insulating film 113 and connected to the source 109. A bit interconnection contact plug 115 is provided inside the contact hole 114 and consists of polycrystalline silicon 115a and metal silicide 115b. A bit interconnection 116 is connected to the bit interconnection contact plug 115 and consists of tungsten nitride 116a and tungsten 116b. An interlayer insulating film 118 with a flat surface covers the bit interconnection 116.
Contact plugs 117 are provided in a predetermined region of the interlayer insulating film 113 and connected to the drains 108 and 112 of the transistors. Capacitance contact holes 119 are formed in a predetermined region of the interlayer insulating film 118 so as to be connected to the contact plugs 117; capacitor contact plugs 120 are provided inside the contact holes 119. A silicon nitride film 121 and an interlayer insulating film 122 are provided over the capacitor contact plug 120 and interlayer insulating film 118.
Capacitors having cylinder structures are provided in a predetermined region of the interlayer insulating film 122. Each capacitor is composed of a lower electrode 124 and a dielectric 125 provided on an inner surface of a cylinder hole 123 formed in the interlayer insulating film 122, and an upper electrode 126 formed to fill the hole. The lower electrode 124 is connected to the capacitor contact plug 120. An interlayer insulating film 127 covers the upper electrode 126. The upper electrode 126 has its partial area led out to a peripheral circuit as a lead-out region 135. The lead-out region 135 is connected to a metal interconnection 134 via a via plug 137 provided in a through-hole 136 formed in the interlayer insulating film 127.
On the other hand, a transistor constituting a peripheral circuit is provided in the second p well 104. The transistor is composed of the source 109, drain 112, gate insulating film 110, and gate electrode 111. Contact holes 128 are formed in predetermined regions of the interlayer insulating film 113 so as to connect to the source 109 and the drain 112. Titanium silicide layers 129 are formed on a source and a drain located at the bottoms of the respective contact holes. Contact plugs 130 are provided inside the respective holes in contact with the respective titanium silicide layers; each of the contact plugs 130 consists of titanium nitride and tungsten. An interconnection layer 131 is provided on each of the contact plugs 130 and consists of tungsten nitride 131a and tungsten 131b. The interconnection layer 131 partly connects to the interconnection 134 via a via plug 133 that fills a through-hole 132 formed through the interlayer insulating film 118, silicon nitride film 121, and interlayer insulating films 122 and 127; the via plug 133 consists of titanium nitride and tungsten.
As is apparent from the above example of a DRAM, many holes are formed in the interlayer insulating films in order to form plugs for the connection between the upper and lower interconnection layers as well as cylinders for capacitors. In particular, for the capacitance contact hole 119 and capacitor cylinder hole 123 formed in the memory cell region, and the through hole 132 formed in the peripheral circuit region, a demand for an increase in integration level has increased aspect ratio, expressed as the ratio of the depth to diameter of the hole, to 15 to 20. This makes it very difficult to machine these holes.
Japanese Patent Laid-Open Nos. 9-45633, 10-50835, and 2001-35921 disclose methods for forming a contact hole and a contact plug.
The above holes are normally formed in interlayer insulating films of silicon oxide. Anisotropic dry etching by high-frequency plasma is used to form holes. To dry etch silicon oxide, it is necessary to break the bond between silicon and oxygen, to cause silicon to react to generate a volatile substance, and to exhaust the substance. Fluorine can be effectively used for reaction with silicon. A source gas may be octaflorocyclobutane (C4F8), octaflorocyclopentane (C5F8), or the like. The source gas is decomposed and excited in plasma to generate fluorine ions. The generated fluorine ions are accelerated by an electric field applied to between the plasma and a stage for the semiconductor substrate. The fluorine ions thus impact the surface of the silicon oxide. The resulting acceleration energy is used to break the bond between silicon and oxygen. The silicon is caused to react to generate volatile silicon fluoride, which is then exhausted. A basic reaction process has been described, and many variations and modifications are actually made to the process. For example, argon gas may be added in order to improve the effect of ions.
If any one of the above holes is to be formed, an etching reaction occurs at the bottom surface of the hole. Accordingly, retention of constant etching characteristics is expected to require the maintenance of the balance between the supply, to the bottom surface, of reaction particles (fluorine ions) contributing to the etching and the exhaust, from the bottom surface, of a reaction product (silicon fluoride) resulting from the etching. However, when the hole becomes deeper to increase the aspect ratio, the reaction product is insufficiently exhausted and is likely to remain at the bottom of the hole. As a result, the remaining reaction product hampers the passage of ions contributing to the etching, causing the etching rate to start decreasing. Finally, the etching is disabled.
Further, the remaining reaction product causes the source gas and reaction product to be polymerized in the hole, with the resulting polymeric substance adhering to the inner wall of the hole. The adhesion of the polymer reduces the hole diameter during etching in a self aligning manner. The hole is thus tapered toward the deeper side and thus shaped like a mortar. This prevents the desired capacitor shape from being obtained, making it difficult to ensure storage capacitance. Further, unfortunately, the contact area of the plug in the hole with the lower conductor decreases to increase contact resistance. The inventors have empirically clarified that this problem becomes actual at an aspect ratio of greater than 10. For example, when a depth of a hole with diameter 0.2 μm increases above 2 μm (aspect ratio: 10), the problem becomes actual. When the depth of the hole becomes 3 μm, the problem becomes significant.